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Dual dielectric tunnel barrier in silicon-rich silicon nitride charge-trap nonvolatile memory

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5 Author(s)
Eunkyeom Kim ; Department of Nano Engineering, University of Seoul, Seoul 130-743, Republic of Korea ; Yim, Taekyung ; An, Seungman ; Won-Ju Cho
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We investigated a tunnel barrier with dual (SiO2 and SiNx) dielectric layers in charge-trap nonvolatile memories to improve the program/erase speed and charge retention characteristics. Threshold voltage shift measurements performed for various stress voltages and time durations revealed that these devices had a large memory window (2–6 V) and long retention time (>10 years). With a decrease in the SiO2 layer thickness, the program speed increased but the erase speed decreased. The change in the program/erase speed and charge retention characteristics with the relative thickness ratio could be attributed to the asymmetric shape of the tunnel barrier. The tunneling currents were explained on the basis of Fowler–Nordheim tunneling and Frenkel–Poole emission in the asymmetric tunnel barrier.

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Applied Physics Letters  (Volume:97 ,  Issue: 22 )