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The design of an optoelectronic arithmetic processor based on permutation networks

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2 Author(s)
Ming-Bo Lin ; Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan ; Oruc, A.Y.

This paper introduces a new concept by which it is possible to design and implement arithmetic processors using permutation networks. To demonstrate this concept, several optoelectronic arithmetic units combining optical directional coupler switches and cyclic permutation networks are designed. The designs show that addition, subtraction, and multiplication can all be performed in O(log n) time in residue code domain and using O(n2) directional coupler switches and gates, where n=log M, and M is the integer range of interest. These arithmetic units also have the capability of concurrent error detection and fault-tolerance, and they can be used to construct constant time inner product processors

Published in:

Computers, IEEE Transactions on  (Volume:46 ,  Issue: 2 )

Date of Publication:

Feb 1997

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