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Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology

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4 Author(s)
Islam, A. ; Dept. of Electron. & Commun. Eng., Deemed Univ., Ranchi, India ; Akram, M.W. ; Pable, S.D. ; Hasan, M.

Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower power dissipation (by 0.11%), higher computing speed (by 4.23%) and lower energy (power delay product) (by 4.33%). The proposed design also offers 4.2% improvement in delay variability and 3.7% improvement in PDP variability at the expense of 2.5% reduction in power variability against process, voltage, and temperature (PVT) variation. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).

Published in:

Advances in Recent Technologies in Communication and Computing (ARTCom), 2010 International Conference on

Date of Conference:

16-17 Oct. 2010