Cart (Loading....) | Create Account
Close category search window
 

An algorithm for exploiting modeling error statistics to enable robust analog optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Singh, A.K. ; Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA ; Lok, M. ; Ragab, K. ; Caramanis, C.
more authors

Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. Fitting over a large region can be grossly inaccurate, and in fact, poor posynomial fit can lead to failure to find a true feasible solution. On the other hand, fitting over smaller regions and then selecting the best region, incurs exponential complexity. In this paper, we advance a novel optimization strategy that circumvents these dueling problems in the following manner: by explicitly handling the error of the model in the course of optimization, we find a potentially suboptimal, but feasible solution. This solution subsequently guides a range-refinement process of our transistor models, allowing us to reduce the range of operating conditions and dimensions, and hence obtain far more accurate GP models. The key contribution is in using the available oracle (SPICE simulations) to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. The key innovation is the explicit link between the fitting error statistics and the rate of the error uncertainty set increase, which we use in a robust optimization formulation to find feasible solutions. We demonstrate the effectiveness of our algorithm on a two benchmarks: a two-stage CMOS operational amplifier and a voltage controlled oscillator designed in TSMC 0.18μm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. We also demonstrate that when utilizing the models with the same level of modeling error, our method yields solutions that meet the constraints while the violations for the standard method were as high as 4- - 5% and larger than 15% for several constraints.

Published in:

Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.