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Resilient microprocessor design for improving performance and energy efficiency

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2 Author(s)
Bowman, K.A. ; Intel Corp., Hillsboro, OR, USA ; Tschanz, J.W.

In this tutorial, a 45nm resilient microprocessor core with error-detection and recovery circuits demonstrates the opportunity for improving performance and energy efficiency by mitigating the impact of dynamic parameter variations. The design methodology describes the additional steps beyond a standard design flow for integrating error-detection and recovery circuits into a microprocessor core. Silicon measurements indicate that the resilient design enables a 41% throughput benefit at iso-energy or a 22% energy reduction at iso-throughput, as compared to a conventional design.

Published in:

Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2010