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Aging analysis at gate and macro cell level

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3 Author(s)
Lorenz, D. ; Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany ; Barke, M. ; Schlichtmann, U.

Aging, which can be regarded as a time-dependent variability, has until recently not received much attention in the field of electronic design automation. This is changing because increasing reliability costs threaten the continued scaling of ICs. We investigate the impact of aging effects on single combinatorial gates and present methods that help to reduce the reliability costs by accurately analyzing the performance degradation of aged circuits at gate and macro cell level.

Published in:

Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2010