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For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware cost as well as delay compared to previous approaches like Horner form or Common Sub-expression Elimination (CSE). This work 1) proposes a formal model for single- and multi-polynomial factorization and 2) handles optimization as a constraint solving problem using an explicit cost function. By this, optimal datapath implementations with respect to the cost function are determined. Compared to recent state-of-the-art heuristics an average reduction of area and critical path delay is achieved.
Date of Conference: 7-11 Nov. 2010