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Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees

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3 Author(s)
Zefu Dai ; Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, M5S 3G4 ; Mark Jarvin ; Jianwen Zhu

Multi-port memory controllers (MPMC) play an important role in system-on-chips by coordinating accesses from different subsystems to shared DRAMs. The main challenge of MPMC design is optimize quality-of-service by simultaneously satisfying different-and often competing-requirements, including bandwidth and latency. While previous works have attempted to address the challenge, the proposed solutions are heuristic and often cannot provide bandwidth and/or latency guarantees. In this paper, we propose a new technique called Credit-Borrow-and-Repay (CBR) that augments a dynamic scheduling algorithm drawn from the networking community, improving it to achieve minimum latency while preserving minimum bandwidth guarantees. Our experiments show that on typical multimedia workloads, the cache response latency can be improved as much as 2.5X.

Published in:

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Date of Conference:

7-11 Nov. 2010