Technology driven architecture for integral parallel embedded computing

The computational structures are not able to scale following the increased number of components offered by the technological development driven by the Moore's law. In order to use efficiently the emerging nanotechnologies new architectural approaches are requested. Thus, new technology driven architectures must be developed. The proposed architecture is designed in this technologically evolving context, to support the increasing computational diversity, complexity and intensity requested in the emergent domain of parallel embedded computing. The resulting physical embodiment has at least two orders of magnitude higher effective GIPS/Watt and GIPS/mm
²
than the currently produced structures. This new architectural approach is based on ConnexArray
^™
technology, already developed and tested on real chips, and on the Bubble-free Embedded Architecture for Multithreading execution model. The paper proposes a computational platform able to manage tens of threads and a number of execution/processing units which starts from tens and goes up to thousands.