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An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:46
,
Issue:
1
)
Date of Publication: Jan. 2011
- Page(s):
- 85 - 96
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11704581
- Digital Object Identifier :
- 10.1109/JSSC.2010.2085970
- Product Type:
- Journals & Magazines
- Date of Publication :
- 03 December 2010
- Date of Current Version :
- 23 December 2010
- Issue Date :
- Jan. 2011
- Sponsored by :
- IEEE Solid-State Circuits Society
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