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Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL

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2 Author(s)
Gary J. Ballantyne ; Haulashore Ltd., Christchurch, New Zealand ; Jifeng Geng

The effect of reference clock jitter on the all-digital phase-locked loop (ADPLL) is considered. The analog-to-digital interface [e.g., a time-to-digital converter (TDC)] is considered only briefly. For the digital-to-analog interface [e.g., a digitally controlled oscillator (DCO)], the analysis is studied in detail. The power spectral density and the integrated power of the ADPLL's output phase noise are assessed for two types of reference clock jitter: 1) small correlated jitter (such as for a typical reference oscillator) and 2) uncorrelated jitter. Uncorrelated clock jitter (intentionally added at the DCO), which is uniformly spread over a sampling interval, is shown to nearly remove the digital images at the ADPLL output, which significantly lowers the minimum reference clock frequency in wireless designs.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 12 )