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A synthesis-based bandwidth enhancement technique for CMOS amplifiers/buffers is presented. It achieves bandwidth-enhancement ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93 for passive network with balanced capacitive loads. By employing a step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Time-domain behavior of the proposed technique is examined. Two prototype amplifier/buffer circuits are designed using lower order passive networks to save chip area and circuit complexity. The test chips are fabricated in a 0.18 μm CMOS process, and measurements verify the frequency- and time-domain analyses. The amplifier provides 18.5 dB gain and 28 GHz bandwidth, while consuming 52 mW power from a 1.8 V supply.
Date of Publication: Feb. 2011