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Expressing dynamic reconfiguration by partial evaluation

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3 Author(s)
Singh, S. ; Dept. of Comput. Sci., Glasgow Univ., UK ; Hogg, J. ; McAuley, D.

Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment

Published in:

FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on

Date of Conference:

17-19 Apr 1996