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SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method

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3 Author(s)
Yamauchi, T. ; RWCP Massively Parallel Syst. Lab., NEC Corp., Kanagawa, Japan ; Nakaya, S. ; Kajihara, N.

This paper describes reconfigurable massively parallel computer system called SOP (Sea Of Processors) that has ability to change its structure and achieves high performance by mapping the control flow and data flow of target algorithms directly on the reconfigurable hardware. SOP system consists of huge number of programmable logic, memory and switch elements. Each logic element is mainly used to map logic/arithmetic operations and control circuits. SOP memory element has ability to process global search, global sorting, heap tree and min/max operations quickly. SOP compiler extracts high degree of parallelism from application programs written in C-language by exploiting operation and function level parallelism using control-data-flow based mapping technique

Published in:

FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on

Date of Conference:

17-19 Apr 1996

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