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Threads vs. caches: Modeling the behavior of parallel workloads

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6 Author(s)
Guz, Z. ; EE Dept., Technion - Israel Inst. of Technol., Haifa, Israel ; Itzhak, O. ; Keidar, I. ; Kolodny, A.
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A new generation of high-performance engines now combine graphics-oriented parallel processors with a cache architecture. In order to meet this new trend, new highly-parallel workloads are being developed. However, it is often difficult to predict how a given application would perform on a given architecture. This paper provides a new model capturing the behavior of such parallel workloads on different multi-core architectures. Specifically, we provide a simple analytical model, which, for a given application, describes its performance and power as a function of the number of threads it runs in parallel, on a range of architectures. We use our model (backed by simulations) to study both synthetic workloads and real ones from the PARSEC suite. Our findings recognize distinctly different behavior patterns for different application families and architectures.

Published in:

Computer Design (ICCD), 2010 IEEE International Conference on

Date of Conference:

3-6 Oct. 2010