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Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates the activity of the IP from the implementation. This allows the ability to easily create a model that can be used with different frequencies, layout and implementation technology. By using data gathered from the RTL a model can be created for high-level simulation that can take into account the technology and characteristics of the FPGA device. The methodology is presented in this paper with a processor and its local memory IP from Xilinx. Compared to estimations made at the RTL level, the resulting model gives accurate results of 15% with three to four order speedups and through different implementations.