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A design of a high PSRR capacitor-less low dropout voltage regulator (LDO) is presented. This circuit is stable for full load current range from 0 to 100mA. A mid frequency zero has been introduced to stabilize the loop. The PSRR achieved was -71.258dB at 130kHz, and more than -40dB upto 650.750kHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 370μV/V and load regulation was just 0.01173%/mA.