A Sub-band Synthesis Filter parallel processor based on Transport Trigger Architecture

The most important stage in MP3 audio processing is Sub-band code/decode, which takes much computational load. In this paper, a solution with configurable processor based on TTA(Transport Trigger Architecture) was proposed to meet with real-time decoding system. According to the algorithm of Subband Synthesis Filter and requirement of accuracy, all the features was custom, such as bus number, bus width, function unit and instruction set. This processor implemented parallel computation by VLIW(Very Long Instruction Word). The FPGA prototype verification results indicated that this solution completed MP3 real-time decoding at the frequency of 30MHz, and SNR was greater than 90db.