By Topic

A Sub-band Synthesis Filter parallel processor based on Transport Trigger Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Zaifeng Shi ; Sch. of Electron. & Inf. Eng., Tianjin Univ., Tianjin, China ; Peng Qiu ; Yong Wang ; Su Wang
more authors

The most important stage in MP3 audio processing is Sub-band code/decode, which takes much computational load. In this paper, a solution with configurable processor based on TTA(Transport Trigger Architecture) was proposed to meet with real-time decoding system. According to the algorithm of Subband Synthesis Filter and requirement of accuracy, all the features was custom, such as bus number, bus width, function unit and instruction set. This processor implemented parallel computation by VLIW(Very Long Instruction Word). The FPGA prototype verification results indicated that this solution completed MP3 real-time decoding at the frequency of 30MHz, and SNR was greater than 90db.

Published in:

Image and Signal Processing (CISP), 2010 3rd International Congress on  (Volume:8 )

Date of Conference:

16-18 Oct. 2010