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High-throughput cost-effective and low-power AES chip design

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3 Author(s)
Yunping Liang ; Key Lab. for Biomed. Inf. & Health Eng., Chinese Acad. of Sci., Shenzhen, China ; Ye Li ; Chengmin Zhang

This paper proposes a high-throughput cost-effective and low-power implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective and low-power, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. In addition, we adopt composite field arithmetic solution to implement SubByte/InvSubByte and byte-level structure to implement MixColumns/InvMixColumns transformation. Considering the high-throughput, we present a mixed pipelining architecture with both inner-round and outer-round pipelining for 10 iteration rounds of operation. The performance is evaluated on SMIC 0.18 μm CMOS technology and the throughput achieves at 8 Gbps with the cost of only 17519 equivalent NAND2 gates, and the power consumption is only 9.7mw.

Published in:

Image and Signal Processing (CISP), 2010 3rd International Congress on  (Volume:9 )

Date of Conference:

16-18 Oct. 2010