Cart (Loading....) | Create Account
Close category search window
 

Transparent logic modeling in VHDL

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Degroat, J.E. ; Ohio State Univ., Columbus, OH, USA

Modeling conventions and VHDL (VHSIC hardware description language) library techniques for transparently mapping between multivalued logic systems without modifying the model itself is described. Using these conventions and the VHDL library system, designers can choose any logic system compatible with the models and use if for simulation. Also described are some of the requirements the multivalued logic systems must satisfy.<>

Published in:

Design & Test of Computers, IEEE  (Volume:7 ,  Issue: 3 )

Date of Publication:

June 1990

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.