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High Level Power and Energy Exploration Using ArchC

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6 Author(s)
Gupta, T. ; CEA, LIST, Gif-sur-Yvette, France ; Bertolini, C. ; Heron, O. ; Ventroux, N.
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With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.

Published in:

Computer Architecture and High Performance Computing (SBAC-PAD), 2010 22nd International Symposium on

Date of Conference:

27-30 Oct. 2010

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