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Processor manufacturers use advances in manufacturing technologies to increase the number of cores on chip in order to scale performance in a cost-efficient manner. As the number of cores scales up, not all cores can be directly connected to the main memory and there is a need for hierarchy, for example, by arranging them in clusters that share L2 caches. This paper focuses on designing cost-efficient L1-L2 interconnects. We discuss performance and power- and area-consumption considerations for a real processor designed in 45-nm technology. We explain the architectures and heuristics developed, including a smart floorplan with instance flips to address interconnect latency, customized decentralized arbitration schemes tailored per transaction type, and heterogeneous Vt device assignment to reduce overall power consumption, taking into account the expected switching factors. These and other methods worked together to achieve high throughput in a power-efficient interconnect that consumes less than 3% of the compute cluster area.