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In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.