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Hermetic wafer-level packaging development for RF MEMS switch

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16 Author(s)
Ferrandon, C. ; CEA-LETI, MINATEC, Grenoble, France ; Greco, F. ; Lagoutte, E. ; Descours, P.
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This paper presents a low temperature (<;;350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements: 1. Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance 2. Electrical connection between both wafers 3. Hermetic sealing under controlled atmosphere with 5+/-0.5 μm gap between the switch and the cap wafers 4. No degradation of the switch performances 5. Low temperature (<;;350°C) packaging process to preserve the moving part materials 6. Electrode and dielectric for electrostatic hold 7. No sticking of the moving contact Two main processes were developed and implemented together: Au-Sn eutectic bonding under atmospheric pressure with 5μm spacers to ensure the gap, and 'post-bonding' TSV. The complete process flow of the cap wafer, bonding and TSV process is presented. The solder material, made of 80wt.%Au and 20wt.%Sn, is only 5μm thick and is electroplated. SEM, XPS, EDX analyses and shear tests have been performed. Hermeticity evaluation tests have been set-up, and a standard leak rate lower than 1.2 × 10-12 mbar.1/s has been demonstrated using the membrane deflexion method. TSV and Au-Sn bump resistance is less than 14mΩ and lOmΩ with a yield of 92% and 98% respectively across the 200mm wafer. The resistance between 2 via is more than 500MΩ at 5V. As to the packaged switch, its insertion losses at 2 GHz are 0.74dB and its off-state isolation is 43.6dB. At last, it has been demonstrated that the substrates resistivity has a great influence on the insertion losses.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010