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Performance requirements such as increased bandwidth and lower power are driving the adoption of 3D ICs designed with through silicon vias. Many companies and research organizations have described the advantages of stacking chips vertically. There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. As companies move from R&D into production the difficult work begins in addressing the issues of design, thermal management, test, and assembly. Different needs and economic factors determine the timing of adoption in each application. Issues in moving to volume production include the installation and qualification of high-volume 300 mm production lines, assembly and test capability, the availability of TSV interposers, and reliability data. This presentation provides an assessment of the infrastructure for 3D TSV and provides an update on the remaining barriers to adoption.