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System integration with eWLB

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4 Author(s)

Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies. The best-known representative of the existing fan-out Wafer Level Packaging Technologies is eWLB (embedded Wafer Level Ball Grid Array), which was invented and introduced by Infineon. eWLB is a true wafer level packaging technology starting with the generation of an artificial wafer. This artificial wafer allows the addition of package area leading to free selectable package size and number of interconnect elements at a given pitch. The driving factors for the implementation of this technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density and the potential for integration of functionality. Two major approaches for system integration on basis of the eWLB technology include side-by-side multi-chip approaches and three-dimensional stacking. For the Multi-Chip eWLB Package several chips were placed close to each other and were encapsulated in one package. Warpage improvement and die shift optimization lead to a process ability for the multi-die wafers comparable to the single die eWLB. Reliability testing indicated no special Multi-Chip Package related fails. We will introduce the results of the development of two-die Multi-Chip eWLB and present the actual reliability results. For the three-dimensional stacking two different ways to generate the interconnection in z-direction were investigated: The placement of pre-fabricated via bars prior to the moldi- - ng of the Reconstituted Wafer and the laser drilling and copper filling of vias in the mold compound. Both principles were investigated with regards to the vertical interconnect and the two-sided processing. Reliability testing showed no special package related failure modes. In this paper we will introduce recent results of the development of both connection strategies for 3D-eWLB, show the challenges of the technology development and present actual reliability results.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010

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