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Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

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10 Author(s)
Ezawa, H. ; Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan ; Togasaki, T. ; Migita, T. ; Yamashita, S.
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Leading-edge LSI products with 40nm logic technology node and beyond are facing the issue of how higher memory bandwidth is reconciled with lower power consumption. Chip stacking of a logic chip on a large-scale DRAM chip, interconnected with each other by fine-pitch bumps, provides a solution to realize a power efficient SiP (System in Package). In this paper, the successful process integration of 10μm pitch Cu redistribution wiring and 40μm pitch SnCu micro-bumping on 300mm wafers, together with chip-on-chip (CoC) joining, has been described in an effort to relinquish embedded DRAM (eDRAM) SoC (System on Chip).

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010