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3D substrate innovation for complex high pin count flip-chip applications

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2 Author(s)
Vern Solberg ; STC-Madison, Tessera USA, 408-321-6000 ; Vage Oganesian

Due to the increased complexity and greatly expanded I/O on today's multiple function semiconductors, IC suppliers have been forced to abandon the traditional wire-bond package assembly, opting instead for the more compact die face-down flip-chip attachment methodology. This face-down, direct attachment method significantly reduces the semiconductors package outline as well as enhancing product performance. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance for the higher-speed processor and ASIC products. The majority of these high pin-count die are being furnished with a very fine-pitch solder bump array contact pattern, many with less than 150 micron pitch. The array pattern on the die element is provided through series of metallization and lithographic processes while the die remain in the wafer level format. This array configured contact pattern enables greater flexibility for die-to-substrate interface routing. Key substrate requirements to be resolved when mounting higher pin count die to a multi-layer glass/epoxy based structure is the ability to overcome irregular solder bump profiles, and the physical affects (warping) of the substrate during high temperature Pb-free soldering. This paper will describe a new raised contact interconnect solution for high-density, multi-layer substrates. The process was specifically developed for mounting very-fine-pitch bumped flip-chip semiconductor die, overcoming both solder bump uniformity concerns and solder process compatibility issues.

Published in:

Electronic System-Integration Technology Conference (ESTC), 2010 3rd

Date of Conference:

13-16 Sept. 2010