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A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole

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5 Author(s)
Do, A.V. ; Nanyang Technol. Univ., Singapore, Singapore ; Boon, C.C. ; Do, A.V. ; Kiat Seng Yeo
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A novel passive mixer architecture is proposed which uses a voltage-mode passive mixer with a tuned output pole. Using this technique, it is shown that the IF section's IIP3 requirements are relaxed by up to 33 dB for the IEEE 802.15.4 standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order channel-select filter is designed in 0.18 μm CMOS technology with a 1-V supply voltage, and post-layout simulations show a 5 dB NF with only 1.7-mW total power consumption.

Published in:

VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP

Date of Conference:

27-29 Sept. 2010

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