Referenced Items are not available for this document.
This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 μm.
Published in:
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Date of Conference: 27-29 Sept. 2010
- Page(s):
- 149 - 154
- Print ISBN:
- 978-1-4244-6469-2
- INSPEC Accession Number:
- 11665296
- Conference Location :
- Madrid
- Digital Object Identifier :
- 10.1109/VLSISOC.2010.5642604
- Product Type:
- Conference Publications
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