Skip to Main Content
New and specific issues arise from the introduction of dynamically reconfigurable components into Multiprocessors Systems (either on or off the chip). Impact of such problems must be evaluated and architectural solutions validated at design time, as early as possible. To do this, one must be able to effectively simulate MPSoC with reconfigurable components at high levels of abstraction (better TLM), and possibly considering the presence of an operating system. In this context, contribution of this paper is twofold: on one hand we analyze the problems arising from concurrent access to reconfigurable resources by different threads in a MPSoC, to which we propose an architectural solution; on the other, we present a framework enabled with dynamic reconfiguration modeling and simulation capabilities, and show its potentials and effectiveness while exploiting it to validate the proposed solution.