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Continuous-time ΔΣ modulators (CTDSMs) with switched-capacitor (SC) feedback digital-to-analog converters (DACs) are relatively less sensitive to clock jitter when compared to converters that use non-return-to-zero feedback DACs. However, as we show in this paper, using an SC DAC can seriously compromise the alias rejection of the modulator, thereby nullifying one of the principal advantages of continuous-time operation. We give an intuitive understanding, as well as an analytical basis, for computing the signal transfer function of CTDSMs with SC DACs. We propose power-efficient circuit techniques to improve alias rejection in such modulators and give experimental results that illustrate some of our ideas.