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Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators

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2 Author(s)
Seung-Chul Lee ; Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Yun Chiu

This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (ΣΔ) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple flnite impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the error coefficients, and an analog-domain PN removal technique is devised to minimize the input signal dynamic-range loss due to the PN circulation in the ΣΔ loop. The behavioral simulation demonstrates that the proposed scheme effectively compensates for the multibit capacitor mismatch errors in the first- and second-order ΣΔ modulators.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 4 )