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A new snubber circuit for high efficiency and overvoltage limitation in three-level GTO inverters

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3 Author(s)
Jae-Hyeong Suh ; Dept. of Electr. Eng., Hanyang Univ., Seoul, South Korea ; Bum-Seok Suh ; Dong-seok Hyun

A new low-loss snubber circuit including an overvoltage clamping circuit for a three-level gate-turn-off (GTO) inverter is presented. The proposed snubber circuit is effective in restriction of the dv/dt and the overvoltage values across each GTO at turnoff and the snubber loss is less than half that of the conventional RCD snubber circuit. In addition, there is no blocking voltage balancing problem between the inner and outer GTOs that occurs in the case where a conventional RCD snubber circuit is used in three-level inverter topology. Experimental results demonstrate that the proposed snubber circuit is very effective for a large capacity three-level GTO inverter

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:44 ,  Issue: 2 )