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A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

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4 Author(s)
Jisu Kim ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Kyungho Ryu ; Kang, S.H. ; Seong-Ook Jung

STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme. Monte Carlo HSPICE simulation results using 65 nm technology model parameters show that the proposed sensing circuit achieves an read access yield of 96.3% with a sensing current of 43.1 uA at a supply voltage of 1.1 V for 32 M bit, whereas the conventional sensing circuit achieves an read access yield of only 0% (81.5%) with a sensing current of 48.0 uA (64.2 uA) at a supply voltage of 1.1 V (1.6 V).

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 1 )

Date of Publication:

Jan. 2012

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