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STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme. Monte Carlo HSPICE simulation results using 65 nm technology model parameters show that the proposed sensing circuit achieves an read access yield of 96.3% with a sensing current of 43.1 uA at a supply voltage of 1.1 V for 32 M bit, whereas the conventional sensing circuit achieves an read access yield of only 0% (81.5%) with a sensing current of 48.0 uA (64.2 uA) at a supply voltage of 1.1 V (1.6 V).