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Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

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5 Author(s)
Bea, J. ; New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan ; Lee, K. ; Fukushima, T. ; Tanaka, T.
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The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 °C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

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Electron Device Letters, IEEE  (Volume:32 ,  Issue: 1 )