A comparative study of CMOS & CNFET based current conveyor at 32nm technology node

This paper presents for the first time the design and comparison of wide bandwidth high performance CMOS and CNFET realization of dual-output second generation current conveyor (CCII±) at 32nm technology node. Until this date, almost all design efforts of CCII± have been directed towards micron range, and the designing aspects at nm range still needs to be explored. Voltage and Current bandwidths, port resistances along with power consumption have been the parameters for comparison. Simulations have been carried out using HSPICE simulator at a reduced power supply of ±0.8V.