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For the most recent CMOS feature sizes (e.g., 90 nm and 65 nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, ZIGZAG & some new techniques like, SLEEPY-STACK, LEAKAGE FEEDBACK approach and SLEEPY KEEPER techniques and, after that to combine the advantages of above written techniques, we propose two novel approaches from simulation study, named "Leakage Feedback with Stack (LFS)" & "Sleep Stack with Keeper (SSK)" which reduces leakage current while saving exact logic state. But based on simulations result with a full adder circuit, "Sleep-Stack with keeper approach" achieves up to 76-80 % less power consumption.
Date of Conference: 17-19 Sept. 2010