Reducing Common-Mode Voltage in Three-Phase Sine-Triangle PWM With Interleaved Carriers

Interleaving pulse width modulation (PWM) waveforms is a proven method to reduce ripple in dc-dc converters. The present study explores interleaving for three-phase motor drives. Fourier analysis shows that interleaving the carriers in conventional uniform PWM significantly reduces the common-mode voltage. New digital signal processor (DSP) hardware supports interleaving directly with changes to just two registers at setup time, so no additional computation time is needed during operation. The common-mode voltage reduction ranges from 36% at full modulation to 67% when idling with zero modulation. Third-harmonic injection slightly reduces the advantage (to 25% at full modulation). However, the maximum RMS common-mode voltage is still less than 20% of the bus voltage under all conditions. The disadvantage of the proposed approach is an increase in current ripple at the switching frequency. Simulations verify the findings. Experiments on a motor drive that uses a commercially available motor-control DSP, connected to a 5 hp motor, agree well with calculations and simulations.