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Design of a Low Voltage-Low Power 3.1–10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology

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3 Author(s)
Simitsakis, P. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece ; Papananos, Y. ; Kytonaki, E.-S.

In this brief, the design of a 3.1 to 10.6 GHz ultra wideband (UWB) RF front-end (RFFE) is presented. It employs a novel low noise common gate amplifier combined with a noise canceling circuit, that provides wideband input matching, high voltage gain and low noise figure in the whole band of operation. It also adopts a passive single balanced direct conversion mixer with a custom designed balun at its local oscillator (LO) input. The RFFE achieves 20.6 dB of voltage gain and it has adequately flat frequency response. Its noise figure is 3-3.8 dB and the CP1 at the input is -19.7 dBm. The circuit consumes only 10.8 mW from a 1.2 V supply and it was designed in IBM's CMOS 65 nm process.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:57 ,  Issue: 11 )

Date of Publication:

Nov. 2010

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