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An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

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2 Author(s)
Cong, J. ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Chang Wu

A novel algorithm, named SeqMapII, of technology mapping with retiming for optimal clock period for K-LUT based FPGAs was recently proposed by P. Pan and C.L. Liu (1996). The time complexity of their algorithm, however, is O(K3n4 log(Kn2) log n) for sequential circuits with n gates, which is too high for medium and large size designs in practice. In this paper, we present three strategies to improve the performance of that approach:(1) efficient label update with single K-cut computation based on the monotone property of labels that we showed for sequential circuits, (2) a novel approach for the K-cut computation in partial flow networks, which are much smaller in practice, (3) SCC (strongly connected component) partition to further speedup the algorithm. In practice, our algorithm works in O(Kn3logn) time and O(Kn) space according to our experimental results. It is 2×104 times faster than SeqMapII-opt for computing optimal solutions and 2 times faster than SeqMapII-heu which uses very small expanded circuits as a heuristic

Published in:

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Date of Conference:

7-9 Oct 1996

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