Research on Configuration Optimization Techniques for Reconfigurable DSP Processor

The paper discusses the configuration optimization scheme of a reconfigurable DSP processor. According to the facts that the coarse-grained reconfigurable computing structures have less configuration information and fast configuration process, a hybrid storage arrangement of data and configuration is proposed. Taking advantages of bus-multiplexing and hybrid storage, the higher memory utilization rate and less on-chip wiring overheads have been achieved.