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Microarchitecture support for reducing branch penalty in a superscaler processor

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4 Author(s)
Sakamoto, M. ; Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Nunomura, Y. ; Yoshida, T. ; Shimazu, Y.

This paper describes the microarchitecture of the 32-bit superscalar microprocessor GMICRO/400 with simple prejump mechanisms and its performance evaluation. GMICR0/400 has six stages of instruction execution pipeline and implements a dynamic branch prediction scheme, executing jump instructions in early stages. For dynamic branch predictions, GMICR0/400 contains a 1-Kbit table which holds a single history bit for each conditional branch instruction. For dynamic return-address predictions, it contains a 16-entry stack, which holds copies of return addresses of return-from-subroutine instructions. Prediction accuracies of the branch history table and the return-address stack are 81.7% and 99.6% for the SPECCINT92 respectively, and achieve a speed-up of 1.27. This performance is 95% of that of an ideal model, with a much more complex prejump mechanism and perfect accuracies

Published in:

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Date of Conference:

7-9 Oct 1996