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Memory hierarchy synthesis of a multimedia embedded processor

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3 Author(s)
Fu, S.T. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Zucker, D.F. ; Flynn, M.

As the disparity between embedded processor and main memory speed widens, and the availability of integration increases, cache hierarchy design plays an increasing role in processor performance. We propose tools for optimizing embedded processor performance under area latency, and performance constraints. As a case study, we explore the cache design space for an Application Specific Embedded Processor (ASEP) targeted for software MPEG1 and MPEG2 decompression. We find that for cache area allocation of greater than 16 mm2, the two level on-chip cache achieves the best performance across all three benchmarks. For cache area under 16 mm2, an on-chip primary cache with a 256 KB off-chip secondary cache performs best. With the addition of two prefetching techniques, Stride Prediction Table and Stream Cache, we are able to further reduce the cache area usage by up to 70% while increasing the performance by up to 17%. The optimized ASEPs are capable of displaying MPEG1 movies at 30 frames per second with cache area usage as low as 6.8 mm2

Published in:

Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on

Date of Conference:

7-9 Oct 1996