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It is shown how floating gate memory cell behaviour during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at high or low temperature bake to provide warning of an impending failure of the capability of memory cells to store data. These tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress time and retention time is established to anticipate retention test results. Experimental results based on an EEPROM test chip are presented in order to show the correlation between retention tests and electrical stress tests.