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Hardware redundancy provides an effective approach to compensate errors online. In addition to that, built-in redundancy can also compensate manufacturing defects and help to increase yield. If both yield improvement and online fault tolerance are addressed, classical models for yield and product quality are no longer sufficient, since a defect-free chip comprises the whole potential of redundancy whereas functional chips with compensated defects may have a strongly reduced fault-tolerance. In this work we focus on TMR systems and analyze the yield and product quality for a desired fault-tolerance level. Both parameters are determined by the probability that manufactured chips show the specified input/output behavior and are able to tolerate additional faults online. Computing the exact values of this probability requires a complex multiple fault analysis. Therefore also lower and upper bounds are presented, and it is shown how the properties of TMR can be exploited to speed up the fault analysis.