By Topic

A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Fukushima, Y. ; Fac. of Sci. & Technol., Sophia Univ., Tokyo, Japan ; Fukushi, M. ; Yairi, I.E. ; Hattori, T.

Due to inevitable node and link failures, developing a fault-tolerant routing control mechanism without using virtual channels (VC) becomes very attractive approach to building large-scale network-on-chips (NoCs). Although several routing control algorithms have been proposed, their complicated routing operations consume a lot of hardware resources, thus making them impractical. In this paper, we propose a novel routing control algorithm for non-VC router of irregular 2D-mesh NoCs. The basic ideas for less implementation space and high-speed routing control are to integrate routing behaviors of the traditional message-based algorithm and to simplify the ring selection. The proposed algorithm is fully analyzed its deadlock-freeness, and is successfully implemented on an FPGA to evaluate the performance. The experimental study shows that the proposed algorithm requires quite small hardware space, while keeping the same routing performance.

Published in:

Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on

Date of Conference:

6-8 Oct. 2010