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SRAM-based FPGAs suffer from soft errors caused by cosmic particles. This paper introduces a new switch box architecture to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch boxes is reduced by means of switch reduction with slight impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The proposed architecture was evaluated on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to single event upsets by about 18% on average compared to the traditional ones. Also, our architecture decreases the probability of ridging and short faults in the switch boxes by about 32% on average.