By Topic

Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Suto, T. ; Grad. Sch. of Sci. & Technol., Hirosaki Univ., Hirosaki, Japan ; Ichijo, K. ; Yoshioka, Y.

Asynchronous circuits possibly have several potential advantages in comparison with synchronous one. In this paper, we attempt to introduce asynchronous circuit design method into the control unit of our 8-bit microprocessor by the burst-mode design method and implemented the asynchronous 8-bit microprocessor with outputs to observe all registers and the program counter by using a standard FPGA development system. And then we evaluate the following four features: the FPGA logic resource usage, the execution time per machine instruction and the power and energy consumption in comparison with the synchronous one using same standard FPGA development system. As future work, we will try to develop the fault tolerant asynchronous microprocessor by using output ports to observe all registers and the program counter within the microprocessor.

Published in:

Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on

Date of Conference:

6-8 Oct. 2010