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Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

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3 Author(s)
Ben Ahmed, A. ; Grad. Sch. of Comput. Sci. & Eng., Univ. of Aizu, Aizu-Wakamatsu, Japan ; Ben Abdallah, A. ; Kuroda, K.

During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared-bus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4×4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.

Published in:

Broadband, Wireless Computing, Communication and Applications (BWCCA), 2010 International Conference on

Date of Conference:

4-6 Nov. 2010

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